A Thin Film Transistor (hereinafter, also referred to as “TFT”) has been used in a switching element formed in a pixel or a driver circuit in an active matrix liquid crystal display device (hereinafter, also referred to as “liquid crystal display”), a Contact Image Sensor (CIS), or a Large Scale Integration (LSI) having SRAM (Static Random Access Memories) However, as growth in size and improvement in resolution have been accompanied in the liquid crystal display, reduction in production costs has become a problem, and reduction in production steps of the TFT also has become a problem, recently.
A technology of producing a liquid crystal display including a monolithic (integrated) circuit in which driving and control circuits for liquid crystal are monolithically formed (integrated), so-called monolithic liquid crystal display (system liquid crystal) has been drawn attention as a measure for solving such a problem. Such a monolithic liquid crystal display can significantly reduce the number of components as well as liquid crystal display assembling production steps and liquid crystal display examination steps. Therefore, use of such a display permits reduction in production costs and improvement in reliability.
In such a monolithic liquid crystal display, polysilicon, and CG silicon (continuous grain boundary crystal silicon) are preferably used as a semiconductor material for forming the TFT. Such semiconductor materials are preferable for forming the monolithic driving circuit and the like, because such materials are excellent in field-effect mobility and can be formed as a film through a low temperature (500° C. or less) process. However, if such a TFT formed of polysilicon and the like has a structure, so-called self-align structure, in which source and drain terminals and a gate terminal overlap with each other, an off-state current is larger than that in a TFT formed of amorphous silicon. Therefore, such a TFT with a self-align structure is not suitably used as a pixel switching element.
Under the above circumstances, TFTs having a structure, so-called offset gate structure, in which the source and drain terminals are positioned in such a way that a distance between each of the source and drain terminals and the gate terminal is several micrometers (this distance is referred to as offset length), have been widely known conventionally (for example, refer to Patent Documents 1 and 2). Such TFTs having an offset gate structure can effectively reduce the off-state current, and therefore can be preferably used as a pixel switching element. As for TFTs forming the driving circuit and the like, a sufficient large on-state current is needed. Therefore, recently, TFTs having a channel length of 2 μm or less is being developed. However, such TFTs having an offset gate structure has little margin for structure. For example, an on-state current is significantly reduced or an effect for reducing the off-state current is significantly deteriorated if the offset length is out of the optimal value. Therefore, such TFTs are not suitable as a TFT having a short channel length which suitably constitutes a driving circuit and the like.
Therefore, for the TFT having a short channel length, a structure, so-called self-align LDD (Lightly Doped Drain structure, in which a low concentration impurity is added (ion-doped) into an offset region in a semiconductor layer, is generally adopted (for example, refer to Patent Document 3). If such a self-align LDD structure is adopted, high reliability can be maintained and simultaneously hot carrier-induced degradation can be reduced even if the channel length is shortened. In addition, the production steps of the TFT can be simplified if the self-align LDD structure is adopted. Therefore, such a self-align LDD structure is particularly important if a TFT having a channel length of 2 μm or less is formed on a large substrate.
A method of forming a semiconductor device including a TFT having a conventional self-align LDD structure is mentioned below with reference to FIGS. 5 (a) to (g).
An insulating film 2, a semiconductor layer 3, a gate insulating film 4, and a gate electrode 6 are first formed on a substrate 1, and then a phosphorus ion 7 is injected into a part of the semiconductor layer 3 for forming an N-type TFT, and a boron ion 12 is injected into a part of the semiconductor layer 3 for forming a P-type TFT. As a result, an N-type low concentration impurity region 8 and a P-type low concentration impurity region 13 are formed (FIGS. 5 (a) and (b)). Then, a first interlayer insulating film 15 is formed (FIG. 5 (c)), and then the first interlayer insulating film 15 and the gate insulating film 4 are anisotropically etched to form a sidewall spacer 16 on side surfaces of the gate electrode and simultaneously the gate insulating film 4 is patterned (FIG. 5 (d)). Then, a phosphorus ion 28 is injected into the N-type low concentration impurity region 8, and a boron ion 19 is injected into the P-type low concentration impurity region 13 using the gate electrode 6 and the sidewall spacer 16 as a mask. As a result, an N-type high concentration impurity region 24 and a P-type high concentration impurity region 26 are formed in a self-align manner, and simultaneously an N-type LDD region 25 and a P-type LDD region 27 are formed in the semiconductor layer 3 below the sidewall spacer 16 in a self-align manner (FIGS. 5 (e) and (f)). Then, a heat treatment is performed to activate the impurity ions 7, 12, 28, and 19 injected into the N-type LDD region 25, the P-type LDD region 27, the N-type high concentration impurity region 24, and the P-type high concentration impurity region 26, respectively, and to repair the crystallinity of the entire semiconductor layer 3. Then, a second interlayer insulating film 21, a contact hole, source and drain wirings 22 are successively formed, and finally a third insulating film 23 is formed (FIG. 5 (g)).
Such a semiconductor device including N-type and P-type TFTs having a conventional self-align LDD structure can provide high reliability and reduce the hot carrier-induced degradation, but such a semiconductor device still has room for improvement in further reduction in the off-state current and simplification of the production steps. In addition, such a semiconductor device has a structure in which the channel region and the high concentration impurity region that is a source or drain region are formed in the same semiconductor layer, and therefore improvement in field-effect mobility in the channel region and reduction in resistance in the source or drain region can not be simultaneously attained, and therefore, such a structure is not suitable for improvement in TFT performances. In such a respect, such a semiconductor has room for improvement.
For this problem, a semiconductor device including: a first conductive type TFT with a LDD (self-align LDD) structure in which a first conductive type low concentration source or drain region is included between a first conductive type high concentration source or drain region and a first channel region; and a second conductive type TFT with an offset structure in which an offset region is included between a second conductive type high concentration source or drain region and a second channel region, is disclosed (for example, refer to Patent Document 4). This semiconductor device can provide high reliability and effectively reduce the off-state current and the hot carrier-induced degradation. However, such a semiconductor device still has room for simplification of the production steps and improvement in the TFT performances.
[Patent Document 1]
    Japanese Kokai Publication No. Hei-06-13404 (pages 2 and 7, FIG. 1)[Patent Document 2]    Japanese Kokai Publication No. Hei-06-140424 (pages 2 and 6, FIG. 1)[Patent Document 3]    Japanese Kokai Publication No. Hei-04-323875 (pages 2, 4, and 7, FIG. 3)[Patent Document 4]    Japanese Kokai Publication No. Hei-09-172183 (pages 16 and 50, FIG. 1)